This section covers my research activities in the field of dynamic verification:

    - Cycle accurate simulation on a multi-processor system,
    - Cycle accurate simulation on a soft-processor array,
    - Simulating designs using Activity dependent, Ordered and Cycle accurate (AOC) C models,
    - Timing driven RTL to RTL partitioning and
    - Multi-FPGA based system prototyping environment.

Cycle accurate simulation on a multi-processor system

This is an ongoing project, where I use an FPGA as the central timing engine, and TI's multicore Keystone II devices, to simulate digital designs. A status report was given at the RSP 2019 Workshop:

T. Strauch, "Combining Simulation and FPGA Based Verification to an Affordable and Ultra-Fast Multi-Billion-Gate Verification System", 30th International Workshop on Rapid System Prototyping, 17-18 Oct. 2019, New York, USA  https://dl.acm.org/doi/10.1145/3339985.3358487.

Cycle accurate simulation on a soft-processor array

For this work, I generated a RISC-V based SHP-ed soft-processor array which I mapped on a Zynq device. After that, designs were partitioned and "simulated" on that array:

T. Strauch, "A Many-Core Solution for the Multi-Objective Challenge in the Field of Dynamic Cycle Accurate Verification", 29th International Conference on Architecture of Computing Systems, ARCS 2016, 4-7 April 2016, Nuremberg, Germany, pp. 1-12, http://ieeexplore.ieee.org/document/7499191/

Simulating designs using AOC C-models

Instead of converting VHDL and Verilog directy into C models, I elaborate the design first and analyse the logic dependencies. This results in an environment, where only active parts of the designs are simulated in an ordered fashion:

T. Strauch, "Deriving AOC C-Models from D&V Languages for Single- or Multi-Threaded Execution using C or C++", 18. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, MBMV 2015, 3-4 March, Chemnitz, Germany, pp. 1-12.

Also submitted to Cornell University Library, 14th July 2018, https://arxiv.org/abs/1807.05442 or here.

Timing driven RTL to RTL partitioning

At times of multi-million gate designs, logic cannot be partitioned based on gate level anymore. Here I propose a register transfer level, timing driven method:

T. Strauch, "Timing Driven RTL-to-RTL Partitioner for Multi-FPGA Systems", 23rd International Conference on Field Programmable Logic and Applications, 2-4 September 2013, Porto, Portugal, pages 1-4, http://ieeexplore.ieee.org/document/6645579/

Multi-FPGA based system prototyping environment

In this paper I show a Multi-FPGA system with equal length routing between all FPGA pins. This has a lot of benefits:

T. Strauch, "Multi-FPGA System With Unlimited and Self-Timed Wave-Pipelined Multiplexed Routing", IEEE Trans. on VLSI, vol. 19. no. 9, Sep. 2011, pp.1549-1558, http://ieeexplore.ieee.org/document/5524056/