for test (DFT)
I am doing research in two DFT related fields:
- RTL ATPG and
- Single Cycle Access structures for
In RTL ATPG we derive stuck-at patterns from RTL. With my
Inherent Faults" solution, you are
able to generate
100% stuck-at coverage on gate level with pattern solely generated on
RTL for the first time. The following paper covers this:
T.Strauch, "A Novel RTL ATPG Model Based on Gate Inherent Faults
(GIF-PO) of Complex Gates",
Methoden und Beschreibungssprachen zur Modellierung und Verifikation
von Schaltungen und Systemen, MBMV 2017, 8-9 February, Bremen, Germany,
Also submitted to Cornell University Library, 15th December 2016, https://arxiv.org/abs/1612.05166.
Cycle Access Structures
Single Cycle Access
Structures - or
better known as "Random Access Structures" replace the classical scan
based approach with a more memory like single cycle read and write
access to individual register lines. In this paper I argue, that my
proposed solution can be seen as a reasonable alternative to existing
Structure for Logic Test", IEEE Transactions on VLSI, vol. 20, no. 5,
May 2012, pp. 878-891, http://ieeexplore.ieee.org/document/5753986.
this paper has been copied over multiple times.