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Motivation
The motivation for
this webpage is to share my work on:
- PDVL: An aspect and transaction oriented Programming, Design
and Verification Language,
- SHP: System Hyper Pipelining,
- as well
as ASIC testing
related
projects (DFT).
News:
Latest IEEE paper on PDVL and
"Dynamic Inside-Out Verification Using Inverse Transactions in TLM" is
now online: https://ieeexplore.ieee.org/document/8524048
I will give a talk on PDVL and
"Dynamic Inside-Out Verification Using Inverse Transactions in TLM" at
the FDL-conference in Munich, http://www.fdl-conference.org
last
modified: 2018/Nov/10 |
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