The motivation for this webpage is to share my work on:

    - PDVL: An aspect-oriented and transaction-level Programming, Design and Verification Language,

    - SHP: System Hyper Pipelining,

    - as well as ASIC testing related projects (DFT).

News:

2025/Feb/27: Uploaded another PDVL example to github. I mapped my CUBE-V (System-Hyper-Pipelined RISC-V) design onto the TinyFPGA BX board (Lattice, ICE40LP8K). I reach 456 MIPS with 32 harts. Check it out here.


2025/Feb/14: My submissions "Non-interfering On-line and In-field SoC Testing" and "Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification" for the 35th International IEEE Workshop on Rapid System Prototyping (RSP) in Raleigh, NC, USA are now online. Cheers !


2024/Aug/15: My submissions "Non-interfering On-line and In-field SoC Testing" and "Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification" were accepted for the 35th International IEEE\ACM Workshop on Rapid System Prototyping (RSP) in Raleigh, NC, USA. Cheers !


2024/June/1: My paper "Deductive Formal Verification of Synthesizable, Transaction-level Hardware Designs Using Coq" is now available: here.


2024/May/8: The recodings of my presentation “MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL” at the 2024 Latch-Up Conference in Boston, USA (April 19-21) is available on youtube: here.


2024/Feb/18: I am looking forward to speaking on the topic “MRPHS: Enabling Transaction-level Deductive Formal Verification Through PDVL” at the 2024 Latch-Up Conference in Boston, USA (April 19-21). Cheers !


2023/Nov/8: My paper "Deductive Formal Verification of Synthesizable, Transaction-level Hardware Designs Using Coq" was accepted for the DATE 2024 Conference. Cheers !


2023/Aug/16: My paper "MRPHS: A Verilog RTL to C++ Model Compiler Using Intermediate Representations For Object-oriented, Model-driven Prototyping" was accepted for the "34th International Workshop on Rapid System Prototyping (RSP)" . Cheers !


2023/Mar/15: It's a TAPEOUT !!!. My CUBE-V CPU (RISC-V) uses WAVE-PIPELINING to better utilize dynamic-interleaved multi-threading. More information here.


2022/Sep/15: I released an application note on "Handling The Caravel Wishbone and Logic Analyzer Interface Hold Time Challenge", which can be found here.


2020/Mar/05: Latest ACM paper on "Combining Simulation and FPGA Based Verification to an Affordable and Ultra-Fast Multi-Billion-Gate Verification System" is now online: here.


2019/Dec/20: RISC-V based Arduissimo project released.


2019/Aug/1: I will give a talk on "Combining Simulation and FPGA Based Verification to an Afforfable and Ultra-Fast Multi-Billion-Gate Verification System" at the Rapid System Prototyping Workshop in October 2019, New York, USA.


2019/June/16: I will give a talk on "An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- And Random-Access-Scan (RAS)" at the Euromicro DSD conference in August 2019, Kallithea, Greece.


2018/July/18: Latest IEEE paper on PDVL and "Dynamic Inside-Out Verification Using Inverse Transactions in TLM" is now online: https://ieeexplore.ieee.org/document/8524048.


2018/May/9: I will give a talk on PDVL and "Dynamic Inside-Out Verification Using Inverse Transactions in TLM" at the FDL-conference in Munich, http://www.fdl-conference.org.